Electrical design and protection coordination solution for Solid-State Transformer (SST) systems

I. Technical Bottlenecks in SST System Integration

Multi-Cabinet Coordination Timing Mismatch

• The power electronic protection response of the power cabinet (SST) operates at the microsecond level, while the relay protection of the high-voltage cabinet operates at the millisecond level. This timing discrepancy creates a "blind zone" in protection coordination during faults, exposing power semiconductor devices to risks of overvoltage and overcurrent damage.

• The inherent breaking time of the high-voltage circuit breaker (30–60 ms) is far slower than the withstand limit of IGBT/SiC devices in the power cabinet (<10 μs). Therefore, the SST system must implement autonomous current-limiting protection before the high-voltage cabinet can act.

RW-SST Series Modular Solid State Transformers

Redundant and Complex Signal Interaction

• A large number of hardwired inter-cabinet signals exist (e.g., disconnector status, earthing switch status, various fault alarms), resulting in complex control cable routing and overcrowded terminal blocks between cabinets.

• The absence of a unified fault classification mechanism leads to ambiguous protection strategies, with response actions for different fault types relying on on-site manual judgment.

Coupling Conflicts in Power Supply and Cooling System Design

• The PT (potential transformer) of the high-voltage cabinet can supply approximately 500 VA of control power, but the cooling fan power consumption can reach the kilowatt level. If fully reliant on external power supply, an additional low-voltage incoming feeder would be required, increasing system cost and footprint.

• Under the forced-air cooling scheme, fan power consumption is not accounted for in overall system efficiency calculations, potentially compromising the SST system's target efficiency of 98%.

II. Core Solutions and Technical Breakthroughs

(A) Three-Tier Collaborative Protection System Design

The SST system implements a three-tier protection architecture with independent operation and graded coordination:

Tier 1 – Hardware Protection (Power Cabinet / SST System)
Executed at the microsecond level (<10 μs) through power electronic modulation for short-circuit current limiting and active IGBT/SiC pulse blocking. This tier takes priority to safeguard power semiconductor devices, acting faster than the high-voltage cabinet protection.

Tier 2 – Electrical Protection (High-Voltage Cabinet)
Operates at the millisecond level (30–60 ms) via five-prevention mechanical interlocking and microcomputer-based protection, enabling autonomous blocking and fault isolation. This ensures equipment safety and automatically disables remote operation under fault conditions.

Tier 3 – Software Protection (Main Control Unit)
Operates at the second level by aggregating signals from both power electronic hardware protection and electrical equipment protection, subjecting them to secondary logic-based judgment. This delivers full-system graded protection management and prevents maloperation or failure to trip.

Key Breakthrough: The "independent protection, graded coordination" mechanism enables microsecond-level hardware protection to act first, filling the millisecond-level "time blind zone" of the high-voltage cabinet. The three tiers coordinate sequentially and serve as backup for one another.

(B) Signal Acquisition and Interface Streamlining Design

Design Principle: "Communication as primary, hardwired points as secondary, streamlined interfaces, redundancy avoidance, resource sharing"

High-Voltage Cabinet Signal Acquisition Optimization

Unified Interconnection Interface Specification for Complete System

• Inputs (DI): Emergency stop button, Local/Remote status, Fault reset — standardized and streamlined to core control points.
• Outputs (DO): Global blocking, Status indicators, Trip output — unified to avoid redundant configuration.

Three-Tier Fault Classification Mechanism

• Level 1 Fault: Emergency pulse blocking — fastest response at microsecond level — executed by power cabinet hardware protection.
• Level 2 Fault: Power-limited operation (50% derating or shutdown) — decided by main control unit software.
• Level 3 Fault: Alarm only; equipment continues running — logged and reported by the main control unit.

(C) Reactor and Short-Circuit Protection Optimization Design

Key Breakthrough: Short-circuit protection of the power cabinet does not depend on the physical impedance of the reactor; it relies primarily on active power electronic modulation for current limiting. The protection speed far exceeds the millisecond-level response of the high-voltage cabinet, ensuring the operational safety of power semiconductor devices.

(D) Coordinated Design of Power Supply and Cooling Systems

Power Supply Coordination

• SST Control Circuit: Powered by the high-voltage cabinet PT (approx. 500 VA) — PT capacity is sufficient, eliminating the need for an additional low-voltage incoming feeder.
• Cooling Fan: Supplied by an independent low-voltage incoming line or SST auxiliary winding (several kW) — must be separately accounted for and incorporated into overall system power capacity planning.

Cooling Efficiency Management

• Challenge: Fan power consumption can reach the kilowatt level, reducing overall system efficiency.
• Solution: Optimize fan operation strategies through intelligent speed control and intermittent operation.
• Target: Overall system efficiency ≥98%.
• Additional Consideration: Proper planning of cooling power tap-off topology prevents efficiency calculation bias, ensuring accurate reflection of overall system losses.

(E) Resource Sharing and Redundancy Design

• Sensor Sharing: High-voltage and low-voltage cabinets share voltage and current sampling points, reducing duplicate acquisition points and lowering hardware and cabling costs.
• IO Resource Reservation: SST acquisition boards reserve DI/DO margins to address potential IO port shortages and facilitate future expansion.
• Control Circuit Streamlining: Consolidate duplicate function points and optimize system architecture for clearer control logic and fewer failure points.

III. Key Technical Parameter Comparison

IV. Engineering Implementation Safeguards

Protection Logic Verification Process

• Phase 1: Consolidate power electronic and electrical protection logic; produce unified documentation

• Phase 2: Output signal type checklist from microcomputer protection to support interface design

• Phase 3: Confirm selection of 400 kHz+ high-bandwidth Hall-effect sensors

• Phase 4: Integrated commissioning and testing of three-tier fault classification protection

Design Coordination Strategies

V. Summary of Solution Advantages

• Seamless Protection Coordination：Microsecond-level hardware protection fills the millisecond-level response blind zone of the high-voltage cabinet; three-tier protection coordinates sequentially.
• Streamlined and Efficient Signal Interface：Communication-primary + hardwired-points-secondary approach; reduces hardwired points by over 60%; simplifies cabling.
• Clear and Controllable Fault Classification：Three-tier fault mechanism defines clear response strategies; eliminates reliance on on-site manual judgment.
• Cost-Effective Resource Sharing：Sensor sharing + IO reservation + control circuit streamlining; reduces hardware costs.
• Coordinated Power Supply and Cooling Optimization：PT power supply + intelligent fan speed control; supports 98% overall system target efficiency.
• 100% Standards Compliance：Fully compliant with State Grid standardized design requirements; unified interfaces and flexible scalability.